Content addressable memory cells perform typical random access memory read and write operations and also have the capability of matching the data being searched for to the data that is stored in the cell. Content addressable memory cells are used in a wide variety of digital systems. In a typical CAM cell each cell is coupled to two data lines, a Column line and a Column-Not line, which are used to input data to the cell during a write operation and output data from the cell during a read operation. The Column line and Column-Not line are also used to search for certain data during a match operation. During a write operation the data lines are forced to the opposite binary state one from the other.
A Write line is coupled to a content addressable memory cell to control the cell during a write operation when data is being stored in the cell. A Match line is also coupled to the cell to signal when data that is being searched for matches data that is stored in the memory cell.
An early content addressable memory cell was presented by Joseph L. Mundy in U.S. Pat. No. 3,701,980 and is shown in FIG. 1. This device is insensitive to electrical noise and cannot operate quickly enough for modern system requirements because the data is stored as a voltage across the gate and source of a single transistor. The effective stored voltage will typically be very small because during a write operation the gate and source of the storage transistor are at approximately the same potential.
Data is written to this cell by activating the Write line 115, which allows the voltages on the Column line 117 and the Column-Not line 118 (collectively referred to as the I/O lines) to be stored on the gates of the transistors 112 and 114, respectively. If the data to be stored is a "1", the Column line will be at a high potential and the Column-Not line at a low potential. When the Write line is charged to a high potential a high voltage will be stored at the gate of the transistor 112 and a low voltage will be stored at the gate of the transistor 114. Because of this the gate and source of the transistor 112 will both be at approximately the same potential and the voltage stored across the gate capacitance will be very small. This cell will need to be refreshed often because the potential stored across the gate capacitance of the storage transistors is small.
Data is read from the Mundy memory cell by activating the Match line 116. If a "1" is stored in the memory cell the voltage at the gate of the transistor 112 will be high and the voltage at the gate of the transistor 114 will be low. Because the gate of the transistor 114 is at a low potential, the Column-Not line 118 is isolated from the Match line. If there is a "1" stored in the memory cell the transistor 112 will have a high potential stored at its gate and the Column line 117 will be connected to the Match line. When the Match line is activated and brought to a high potential the Column line will follow, signalling that the data stored is a "1."
If the information stored in the memory cell is the inverse of the information on the I/O lines, the Match line 116 will be driven to a low potential. But, if the information stored in the memory cell is not the inverse of the information on the I/O lines the Match line will be charged to a high potential. Thus, if a "1" is stored in the memory cell the voltage at the gate of transistor 112 will be high and the voltage at the gate of the transistor 114 will be low. If the data to be searched for is also a "1", the Column line will be at a high potential and the Column-Not line will be at a low potential. Because the-voltage at the gate of the transistor 112 is high, the Match line will be charged high, indicating a match between the stored data and the data on the I/O lines.
In the case where the data to be searched for is a "0", the Column line 117 voltage will be low and the potential of the Column-Not line 118 will be high. Because the voltage at the gate of the transistor 114 is low the Match line 116 will discharge. This signals that the data stored in the memory cell did not match the data that was sought.
A second content addressable memory cell was presented by Jon P. Wade in U.S. Pat. No. 4,831,585 and is shown in FIG. 2. This design improved the Mundy memory cell by cross-coupling the write transistors to the storage transistors so that a high voltage is always stored on a transistor whose source is at ground. This cross-coupling increased the voltage stored on these transistors, and thus increased the storage time and the reliability. This cell does not require refreshing as often as the Mundy cell.
During a Write operation, the Write line 216 must be activated and brought to a high potential. By activating the write line, the transistor MW1 is allowed to store the data from the Column line 246 on the gate of the transistor MS1 and the transistor MW0 will store the data from the Column-Not line 248 on the gate of the transistor MS0. If a "1" is to be stored in the memory cell the Column line will be at a high potential and the Column-Not line will be at a low potential. When the Write line is activated the transistors MW1 and MW0 will connect the Column line to the gate of the transistor MS1 and the Column-Not line to the gate of the transistor MS0, respectively. This will store a high potential on the gate of the transistor MS1 and a low potential on the gate of the transistor MS0. When the Write line is deactivated the gates of the transistors MS1 and MS0 will be isolated from the Column line and the Column-Not line, respectively, such that the data will be stored at the gates of those transistors until another write operation is performed.
Data is read from this cell in the same fashion that data can be read from the Mundy cell. To read the data stored in the memory cell the Match line 234 must be charged to a high potential and the Column line 246 and the Column-Not line 248 must both be discharged to a low potential. If a "1" is stored in the memory cell the voltage at the gate of the transistor MS0 will be low, isolating the Column line from the Match line, and the voltage at the gate of the transistor MS1 will be high. Because the transistor MS1 is "on" the Column-Not line will be connected to the Match line and raised to a high potential. This data must then be inverted such that, during a read operation the raising of the Column-Not line to a high potential will signal that a "1" is stored in the memory cell and the raising of the Column line to a high potential will signal that a "0" is stored in the memory cell. Because of the characteristics of these N-channel transistors and the I/O lines, it takes a greater amount of time to raise the potential of the I/O lines to a high potential than it would to discharge an I/O line to a low potential through these devices.
To perform a search operation in this memory cell the Match line 234 must be kept at a high potential. The data to be searched for must also be inverted, as in the Mundy cell, before it is applied to the Column line 246 and the Column-Not line 248. If the stored data is the same as the inverted data to be searched for, no current will flow through the "on" transistor. But, if the stored data is not the same as the inverted data to be searched for, current will flow from the Match line through the "on" transistor to the respective I/O line signalling that the data did not match. Match line performance in this cell is limited by the gate-to-source voltage of the discharging transistor, which is initially depleted by the threshold voltage and is further coupled downward by the falling potential of the I/O line it is coupled to.
If a "1" is stored in the memory cell the gate of the transistor MS1 will be at a high potential and the gate of the transistor MS0 will be at a low potential. If the data to be searched for is also a "1", after the inverse is applied to the Column line 246 its voltage will be low and the potential of the Column-Not line 248 will be high. Because the data stored is a one the transistor MS1 will be turned on, connecting the Column-Not line to the Match line 234 and the transistor MS0 is turned off isolating the Column line from the Match line. Since both the Column-Not line and the Match line are at a high potential, no current will flow through the Column-Not line and a Match will be detected.
If the data to be searched for is a "0", after the inverse is applied to the Column line 246 its voltage will be high and the potential of the Column-Not line 248 will be low. Because the data stored is a "1" the transistor MS1 will still be turned on, connecting the Column-Not line to the Match line 234 and the transistor MS0 is turned off isolating the Column line from the Match line. Since the Match line is at a high potential and the Column-Not line is at a low potential current will flow from the Match line through the Column-Not line, signalling that the data did not match.
What is needed is a content addressable memory cell having the ability to store a data bit with a sufficiently high gate-to-source voltage to avoid noise sensitivity. Further, a cell is needed which avoids the time delay associated with charging an I/O line during a read operation through N-channel devices in order to achieve access time requirements necessary for a modern system.